Institution-Based Encoding and Verification of Simple UML State Machines in CASL/SPASS

نویسندگان

چکیده

We present a new approach on how to provide institution-based semantics for UML state machines. Rather than capturing machines directly as an institution, we build up logical framework \(\mathcal {M}^{\downarrow }_{\mathcal {D}}\) into which can be embedded. A theoroidal comorphism maps the \(\textsc {Casl}\) institution. This allows symbolic reasoning By utilising heterogeneous toolset {HeTS}\) that supports {Casl}\), broad range of verification tools, including automatic theorem prover {Spass}\), combined in analysis single machine.

برای دانلود باید عضویت طلایی داشته باشید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

An Institution for Simple UML State Machines

We present an institution for UML state machines without hierarchical states. The interaction with UML class diagrams is handled via institutions for guards and actions, which provide dynamic components of states (such as valuations of attributes) but abstract away from details of class diagrams. We also study a notion of interleaving product, which captures the interaction of several state mac...

متن کامل

Interactive Verification of UML State Machines

We propose a new technique for interactive formal verification of temporal properties of UML state machines. We introduce a formal, operational semantics of UML state machines and give an overview of the proof method which is based on symbolic execution with induction. Usefulness of the approach is demonstrated by example of an automatic teller machine. The approach is implemented in the KIV sy...

متن کامل

Verification of UML State Diagrams Using Concurrent State Machines

Numerous research projects are done in academia as well as in industry aimed to support the design process based on UML and Model Driven Architecture with new methods and tools that would help to verify both static and dynamic aspects of UML model, to generate the code from it etc. Much attention is paid to the verification of system’s behavior by model checking. In a research project done in t...

متن کامل

Execution and Verification of UML State Machines with Erlang

Validation of a system design enables to discover specification errors before it is implemented (or tested), thus hopefully reducing the development cost and time. The Unified Modelling Language (UML) is becoming widely accepted for the early specification and analysis of requirements for safety-critical systems, although a better balance between UML’s undisputed flexibility, and a precise unam...

متن کامل

Semantics of UML State Machines

The abstract syntax and semantics of a simplified subclass of UML state machines is defined. 1 UML State Machines We illustrate the main concepts of UML state machines by a simple UML model of an automatic teller machine (ATM), shown in Fig. 1: The class diagram in Fig. 1(a) specifies an (active) class Bank. Classes define attributes, i.e., local variables of its instances, and operations and s...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: Lecture Notes in Computer Science

سال: 2021

ISSN: ['1611-3349', '0302-9743']

DOI: https://doi.org/10.1007/978-3-030-73785-6_7